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論文一覧
1984年 6月
東京大学工学系研究科
工学博士
博士論文「改善した一次元半導体素子モデルとその素子設計及び動作解析への応用」
筆頭論文
1. A.Nakagawa, "
One dimensional device model
of the npn bipolar transistor including heavy doping effects under Fermi
statistics
",
2. A.Nakagawa et al., "
Computer aided design
consideration on low loss p-i-n diodes
", IEEE Trans. On Electron Devices, ED-28,
pp.231-237(1981)
3. A.Nakagawa, "
Numerical analysis on abnormal
thyristor forward voltage increase due to heavy doping in gated p-base
layer
", Solid State
Electron., Vol.24, pp.455-459(1981)
4. A. Nakagawa et al., "High
voltage low on-resistance VDMOS FET
" Jap. J.
Appl. Phys. Vol.21 supplement 21-1, pp.97-101(1982)
5. A.Nakagawa et al., "A study on GTO turn-off failure mechanism- a time
and temperature-dependent 1-D model analysis", IEEE Trans.
On Electron Devices, ED-31, pp.273-279(1984)
6. A.Nakagawa et al., "
7. A.Nakagawa, "A
time- and temperature-dependent two-dimensional simulation of GTO turnoff
process II - inductive load case
"
8. A.Nakagawa et al.,"600- and 1200V bipolar-mode MOSFETs with high
current capability" IEEE Electron Device Letter, EDL-6,
pp.378-380(1985)
9. A.Nakagawa, "Current status for bipolar-mode MOSFETs(IGBT)", Denshi Tokyo, No.25, pp.114-116(1986)
10. A.Nakagawa, "Numerically predicted on-resistance for 450-V GaAs power SITs operated in the
bipolar mode
" IEEE Trans. on Electron Devices, ED-33,
pp.167-170(1986)
11. A.Nakagawa et al., "Safe operating area for 1200-V non-latch-up
bipolar-mode MOSFETs", IEEE Trans. on Electron Devices,
ED-34, pp.351-355(1987)
12. A.Nakagawa et al., "Breakdown voltage enhancement
for devices on thin film silicon layer/silicon dioxide
film
", IEEE Trans. On Electron
Devices, ED-38, pp.1650-1654(1991)
筆頭学会発表
1. A.
Nakagawa et al, "A
time- and temperature- dependent simulation of the GTO turn-off process",
1982 IEEE IEDM Tech. Digest, pp.496-499
2. A.
Nakagawa et al.,
High voltage bipolar-mode MOSFETs with
high current capability
", Ext. Abst. of SSDM,
pp.309-312(1984)
3. A. Nakagawa et al., "Non-latch-up
1200V 75A bipolar-mode MOSFET with large ASO ",
1984 IEEE IEDM Tech Digest, pp.860-861
4. A.
Nakagawa et al., "Experimental
and numerical study of non-latch-up bipolar-mode MOSFET characteristics
" 1985 IEEE IEDM Tech Digest, pp.150-153
5. A. Nakagawa et al., "1800V non-latch-up bipolar-mode MOSFETs(IGBT) fabricated by silicon wafer direct
bonding
",, Ext. Abst. of
SSDM, pp.89-92(1986)
6. A. Nakagawa et al., "1800V bipolar-mode MOSFETs-
a first application of silicon wafer direct-bonding to a power
device
" 1986 IEEE IEDM Tech Digest,
pp.122-125
6A. A.
Nakagawa et al., "CURRENT STATUS FOR BIPOLAR-MODE MOSFETS(IGBT)" Denshi Tokyo,
IEEE TOKYO SECTION, pp.114-116(1986)
7. A. Nakagawa et al., "Improved bipolar-mode MOSFETs(IGBT) with
self-aligning technique and wafer-bonding(SDB)- Why is the bipolar-mode MOSFET
SOA large?
-", Ext. Abst. of SSDM,
pp.43-46(1987)
8. A.
Nakagawa, S. Nakamura,
and T. Shinohe, “
RAPID CONVERGENCE BIPOLAR-MOS COMPOSITE DEVICE MODEL --TONADDEII--
and its APPLICATION TO BIPOLAR-MODE MOSFETS (IGBT)
” Proc. of NASCODE V, 1987
9. A.
Nakagawa et al., "Two
types of 500V double gate lateral N-ch bipolar-mode MOSFETs in dielectrically
isolated p- and n- silicon island ", 1988 IEEE
IEDM Tech Digest, pp.817-820
10. A. Nakagawa et al, "High voltage
new driver IC technology" PESC'88 RECORD., pp.1325-1329
11. A. Nakagawa, "Numerical Experiment for 2500V Double gate bipolar-mode MOSFETs and analysis for large safe operating area
", PESC'88 Record, p84
12. A. Nakagawa, and S. Nakamura, “Application of General Purpose Power BiMOS Simulator TONADDEII to Double GATE Lateral
Bipolar-Mode MOSFET Design
”, Proceedings of
1988 International Symposium on Power Semiconductor Devices
13. A. Nakagawa, Y. Yamaguchi,
and K. Watanabe, “
500
V Lateral Double Gate Bipolar-Mode MOSFET (DGIGBT) Dielectrically Isolated by
Silicon Wafer Direct-Bonding (DISDB)
”, Extended Abstract of the 20th(1988 International)
Conference on Solid State Devices and Materials, Tokyo, pp.33-36
(1988)
14. A. Nakagawa et al., "Application of dielectric
isolation technique based on silicon direct-bonding to power ICs" Ext. ABSTRACT
of ECS, p.421(1989)
15. A. Nakagawa et al., "Application of dielectric isolation technique based on silicon
wafer direct-bonding to power ICs", Proc. of Symposium on High Voltage and
SMART POWER ICs edited by M.A.Shibib (The
Electrochemical Society, INC), pp.271-277
16. A.
Nakagawa et al, "Turn-on mechanism of 2500V
MOS assisted gate thyristor (MAGT)
", 1990 IEEE IEDM
Tech. Digest, pp.811-814
17. A.
Nakagawa et al., ""
New
500V output device structure on silicon oxide film’’,
Proc. of ISPSD, pp.97-101(1990)
18.
中川明夫 「小特集：電力用半導体デバイスの高性能化・インテリジェント化の動向 VI. インテリジェントパワーIC」 電気学会誌 平成２年２月号抜刷 Journal
of IEE of Japan Vol. 110, No.2, Feb (1990)
19. A. Nakagawa, and K.Sato “
Bipolar MOS Power Device Simulator TONADDEIIC Taking
into Account External Circuit” Proceedings of 1990 International
Symposium on Power Semiconductor Devices & ICs
20. A.
Nakagawa et al., "A
novel high voltage device structure on thin SOI for VLSIs",
Ext. Abst. of 1991 SSDM, p.731
21. A. Nakagawa et al., “
Impact
of dielectric isolation technology on power ICs(Invited) ",
Proc. of ISPSD, pp.16-21(1991)
22. A.
Nakagawa, "Prospects of
high voltage power ICs on thin SOI(Invited paper) " 1992 IEEE IEDM
Tech Digest, pp.229-232
23. A.
Nakagawa et al., "
500V
three phase inverter ICs based on a new dielectric isolation technique
",
Proc. of ISPSD, p.328(1992)
24. A. Nakagawa, T.Matsudai,
and I.Omura “
Dynamic Shielding of Substrate Bias Effects on Electrical
Characteristics of High Voltage IGBT on SOI
”, Extended
abstract of the 1992 International Conference on Solid State Devices and
Materials pp137-139 (1992)
25. A. Nakagawa et al., "200C high
temperature and high speed operation of 440V lateral IGBTs on 1.5mm
thick SOI " 1993 IEEE IEDM Tech Digest, pp.687-690
26. A. Nakagawa, "High
Voltage SOI Technology(Invited) "
EXTENDED ABSTRACTS, VOLUME 95-1, SPRING
MEETING, RENO, NEVADA, MAY 21-26, p.573(1995)
27. A.
Nakagawa, "Recent advances in high voltage SOI technology for motor control
and automotive applications
", Proc. of 1996 BCTM, pp.69-72
28. A.
Nakagawa et al., “New High
Voltage SOI Device Structure Eliminating Substrate Bias Effects
”, 1996 IEEE IEDM TechDigest, p.477
29. A. Nakagawa et al., “Design Optimization of 500V SOI High Speed Diodes”,
PCIM INTER’98
30. A. Nakagawa et al., “
Improvement
in Lateral IGBT Design for 500V 3A One Chip Inverter ICs ”
Proc. of ISPSD’99, pp.321-324.(1999)
31. A. Nakagawa et al., “
Improved 20V Lateral Trench Gate Power MOSFETs with
Very Low On-Resistance of 7.8mWmm2”
Proc. of ISPSD,pp.47-50(2000)
32. A. Nakagawa, “Single Chip Power Integration ---High Voltage SOI and Low Voltage
BCD---
“, Proc. of CIPS, pp.8-15(2000)
33. A. Nakagawa et. al, “Design Optimization of 500V 1A SOI 1 Chip Inverter
ICs”, Proc. of PCIM China 2003, pp.94-98(2003)
34. Akio Nakagawa, Tomoko Matsudai,
Tadashi Matsuda, Masakazu Yamaguchi and Tsuneo Ogura, “
MOSFET-mode
Ultra-Thin Wafer PTIGBTs for Soft Switching Application--- Theory and
Experiments ”, Proc. of ISPSD, pp.103-106(2004)
35. Akio Nakagawa, "
Theoretical
Investigation of Silicon Limit Characteristics of IGBT ",
Proc. of ISPSD, pp.5-8(2006)
36. Akio Nakagawa, ”
Evolution of Silicon Power Devices and Challenges to
Material Limit”, PROC. 25th INTERNATIONAL
37. Akio Nakagawa, Yusuke Kawaguchi and Kazutoshi
Nakamura, “Achieving
Material Limit Characteristics in Silicon Power Devices”, 2007
International Workshop on the Physics of Semiconductor Devices, pp.762-767
38. Akio Nakagawa, Yusuke Kawaguchi and Kazutoshi
Nakamura,” Power Device
Evolution Challenging to Silicon Material Limit”, Extended
Abstracts of the 2008 International Conference on Solid State Devices and
Materials, Tsukuba, 2008, pp. 732-733
39. Akio Nakagawa, Yusuke Kawaguchi and Kazutoshi
Nakamura, “Silicon Limit Electrical Characteristics of Power
Devices and ICs”, Proc. ISPS2008
40. A.
Nakagawa,
"Recent advancement in high voltage power devices and ICs; Challenges to achieve
silicon limit characteristics," Proc. of Technical Program, VLSI Technology, Systems and Applications,
2008. VLSI-TSA 2008, p.103(2008)
41.
中川明夫、倉田衛 「電力素子開発への数値計算の応用」 電気学会雑誌 103巻10号
42.
中川明夫 「パワーデバイスと複合デバイスのシミュレーション」 電学論Ｃ、107巻、6号、昭62、p.525(1987)
43.
中川明夫、川口雄介 「電源用パワーデバイスの技術動向 」 電気学会誌
平成17年12月号（125巻12号）、p.758(2005)
44. 中川明夫 「IGBT発展の経緯と限界特性 」
先進パワー半導体分科会 第一回講演会予稿集、p.8(2014)
45. A. Nakagawa et al., "High Voltage Low
On-Resistance VDMOS FET" Digest of Tech. Papers The 13th Conf. of Solid State
Devices, Tokyo, p. 81(1981)
46. 中川明夫 「パワーエレクトロニクスの中心的なデバイスになったIGBTの実用化」 えれきてる
47. 中川明夫 「IGBT開発の経緯（１）」＆「IGBT開発の経緯（２）
」
半導体産業人協会 ENCORE誌2009年4月号、5月号
共著書
1. 「パワーデバイス・パワーＩCハンドブック」電気学会高性能高機能パワーデバイス・パワーＩＣ調査専門委員会編 コロナ社
2. Wai-Kai Chen, “THE VLSI HANDBOOK”
CRC PRESS, ISBN 0-8493-8593-8
3. 「インテリジェントパワーＩＣ／インテリジェントパワーモジュール 実装設計技術」ミマツデータシステム
4. スイッチング電源技術用語辞典（共著） 日刊工業新聞社
5. 「世界を動かすパワー半導体」
オーム社
その他の共著論文
1. M.Azuma, A.Nakagawa,
and K.Takigami “High
Power Gate Turn-Off Thyristor” Proceedings of the 9th
Conference on Solid State Devices, Tokyo, Japanese Journal of Applied Physics,
Vol.17 pp.275-281 (1978)
2. H.Ohashi, and A.Nakagawa “A
STUDY ON GTO TURN-OFF FAILURE MECHANISM
” IEEE IEDM Tech. Digest, December (1981)
3.
M.Kurata, M.Azuma, H.Ohashi, K.Takigami,
A.Nakagawa, and K.Kishi “GATE TURN-OFF THYRISTORS” Semiconductor Devices for
Power Conditioning Edited by Roland Sitting and P.Roggwiller (Plenum Publishing
Corporation, 1982)
4. K.Watanabe, A.Nakagawa, and H.Ohashi, “Design Optimization of 100V Resistive Dield Plate
” THE TRANSACTION OF THE IECE OF
JAPAN, Vol. E69, No.4 pp.246-247 April (1986)
5. H.Ohashi, K.Furukawa,
M.Atsuta, and A.Nakagawa, “Study of Si-Wafer Directly Bonded Interface Effect on Power Device
Characteristics
” PROCEEDINGS OF THE IEDM-INTERNATIONAL ELECTRON DEVICES
MEETING,
6. M.Atsuta, T.Ogura, A.Nakagawa,
and H.Ohashi, “An NPN Transistor Fabricated by Silicon Wafer Direct-Bonding
”, Extended Abstract of the
19th Conference on Solid State Devices and Materials, Tokyo, pp.47-50 (1987)
7. T.Ogura, M.Kitagawa, H.Ohashi,
and A.Nakagawa, “6000V Gate Turn-Off Thyristor (GTO) with N-Buffer and New Anode
Short Structure
” Extended Abstract of the 19th
Conference on Solid State Devices and Materials, Tokyo, pp.63-66
(1987)
8. T.Ogura, A.Nakagawa,
K.Takigami, M.Atsuta, and Y.Kamei, “6000V Double Gate GTOs
”, Extended Abstract of the 20th(1988 International) Conference on Solid
State Devices and Materials, Tokyo, pp.37-40 (1988)
9.
中村慎、中川明夫 「２次元複合デバイスシミュレータのための高速反復行列解法」電学論 C、１０８巻５号、昭６３
10.
T.Ogura, A.Nakagawa, K.Takigami, M.Atsuta, and Y.Kamei, “High
Frequency 6000 V Double Gate GTOs
”, International Electron
Device meeting pp.610-613 (1988)
11. T.Shinohe, A.Nakagawa, Y.Minami,
M.Atsuta, Y.Kamei, and H. Ohashi, “ULTRA
HIGH di/dt 2500 V MOS ASSISTED THYRISTORS (MAGTs) for HIGH REPETITION EXCIMER
LASER SYSTEM
”, IEDM, pp.301-304
(1989)
12. K.Furukawa, and A.Nakagawa, “APPLICATIONS OF THE WAFER
DIRECT-BONDING TECHNIQUE TO ELECTRON DEVICES”, Applied Surface Science
41/42 North Holland pp.627-632 (1989)
13. I.Omura, and A.Nakagawa, “A
Breakdown Voltage Simulator TONADDEIIB” Proc. of NASCODE-VI, p.372, 1989
14.
K.Furukawa, A.Nakagawa,
K.Tanzawa, and N. Kawamura, “
SMALL WARPAGE DIELECTRICALLY ISOLATED WAFER FOR POWER
ICs BY SILICON WAFER DIREC-BONDING” Proceedings of 1990
International Symposium on Power Semiconductor Devices & ICs Tokyo,
pp.180-185 (1990)
15. Y.Yamaguchi, A.Nakagawa, N.Yasuhara, K.Watanabe, and
T.Ogura, “New Anode Structure for High Voltage Lateral IGBTs
” Extended Abstract of the 22nd
(1990 International) Conference on Solid State Devices and Materials pp.677-680
(1990)
16. T.Shinohe, A.Nakagawa,
Y.Minami, M.Atsuta, Y.Kamei, and H. Ohashi, “
ULTRA HIGH di/dt PULSE
SWITCHING OF 2500 V MOS ASSISTED GATE-TRIGGERED THYRISTORS
(MAGTs)
” Proceedings of 1990
International Symposium on Power Semiconductor Devices & ICs
17. T.Ogura, A.Nakagawa,
M.Atsuta, Y.Kamei, and K.Takigami, “
HIGH FREQUENCY 6000 V DOUBLE GATE GTOs WITH BURIED
STRUCTURE” Proceedings of 1990 International Symposium on
Power Semiconductor Devices & ICs Tokyo, pp.252-255 (1990)
18. N.Yasuhara, A. Nakagawa, and K.Furukawa “
SOI Device Structures Implementing 650 V High Voltage
Output Devices on VLSIs
” 1991 IEEE IEDM Tech Digest
19. A.Yahata and
A.Nakagawa, “Electron Traps on Si p+nn+ Diodes Created by 10 MeV Electron
Irradiation”, Japanese Journal of Applied Physics, Vol.30, No.6, pp1194-1195
June (1991)
20.
T.Ogura, M.Kitagawa, A.Nakagawa, and H.Ohashi, “6000-V Gate Turn-Off Thyristors (GTO’s) with n-Buffer and New
Anode Short Structure
”, IEEE TRANSACTION ON ELECTRON DEVICES, Vol. 38,
No.6 June (1991)
21. I.Omura, A.Nakagawa, “
A Rapid Convergence
Device-Circuit Complete Coupled Simulation
”, 1991 International Workshop on VLSI Process and
Device Modeling (1991 VPAD)
22. A.Yahata, Y.Yamaguchi,
A.Nakagawa, and H.Ohashi, “
NEW METHOD OF CARRIER LIFETIME MEASUREMENT FOR
ACCURATE POWER DEVICE SIMULATION” Proc. of ISPSD, pp.171-175
(1991)
23. T.Matsudai, and A.Nakagawa, “
SIMULATION OF A 700
HIGH-VOLTAGE DEVICE STRUCUTRE ON A THIN SOI----SUNSTRATE BIAS EFFECT ON SOI
DEVICES---
“,
Proceedings of 1992 International Symposium on Power Semiconductor Devices
&ICs, Tokyo, pp272-277 (1992)
24. M.Kitagawa, K.Matsushita,
and A.Nakagawa, “
HIGH VOLTAGE (4 kV) EMITTEER
SHORT TYPE DIODE (ESD)
”
Proceedings of 1992 International Symposium on Power Semiconductor Devices
&ICs,
25. I.Omura, A.Nakagawa, “
4.5 kV GTO Turn-off Failure
Analysis under an Inductive Load Including Snubber, Gate, Circuit, and Various
Parasitics
”
Proceedings of 1992 International Symposium on Power Semiconductor Devices
&ICs,
26. K.Nakayama, and A.Nakagawa, “
A Study on IGBT’s Steady State
SOA with Newly Developed Simulation
” Proceedings of 1992 International Symposium on Power
Semiconductor Devices & ICs, Tokyo, pp.34-38
27. T.Ogura, A.Nakagawa, “IGBT Mode Turn-Off Thyristor (IGTT)
Fabricated on SOI Substrate
” IEDM pp.241-244
(1992)
28. T.Ogura, A.Nakagawa, M.Atsuta,
Y.Kamei, and K.Takigami, “High-Frequency 6000-V Double-Gate GTO’s
” IEEE TRANSACTION ON
ELECTRON DEVICES. VOL.40. No.3, March
1993
29. N.Yasuhara, T.Matsudai, and A.Nakagawa, “SOI
Layer Thickness and Buried Oxide Thickness Dependencies of High Voltage Lateral
IGBT Switching Characteristics
” Extended
abstracts of the 1993 International Conference on Solid State Device and
Materials, Makuhari, pp270-272
(1993)
30. M.Kitagawa, I.Omura, S.Hasegawa, T.Inoue, and A.Nakagawa, “A
4500 V Injection Enhanced Insulated Gate Bipolar Transistor (IGBT) Operating in
a Mode Similar to a Thyristor” International Electron Devices meeting (IEDM)
pp679-682 (1993)
31. I.Omura, N.Yasuhara, A.Nakagawa, and Y.Suzuki, “Numerical Analysis of SOI IGBT switching characteristics?Switching
speed enhancement by reducing the SOI thickness
”, 5th International Symposium on Power Semiconductor Devices and IC’s
pp248-253(1993)
32. K.
Matsushita,
33. H.
Funaki, A. Nakagawa et al., “Numerical Aanalysis of
Silicon carbide Schottky Diodes and Power
MOSFETs”, , Proc., of
ISPSD, pp.212-217(1993)
34. I.Omura, A.Nakagawa, “Numerical Prediction for 2GHz RF Amplifier of SOI Power
MOSFET
” Extended Abstract of the 1994 International Conference on
Solid State Devices and Materials, Yokohama, pp.292-294
(1994)
35. M.Kitagawa, A.Nakagawa, and
I.Omura, “Injection Efficiency Enhancement in Dynamic Trench Gate Emitter
(DTGE) for 4500 V MOS Gate Transistor (IEFGT)
” Extended
Abstracts of the 1994 International Conference on Solid State Devices and
Materials, August 23-26 pp.760-762 (1994)
36. T.Matsudai, Y.Yamaguchi, N.Yasuhara, and A.Nakagawa,, “Thin SOI IGBT leakage
current and a new device structure for high temperature
operation”
Proc. of the 6th Internat. Symposium on Power
Semiconductor Device &IC’s.
37. T. Matsudai, M. Kitagawa and A. Nakagawa, “A trench Gate Injection
Enhanced Lateral IEGT on SOI”, Proc., of ISPSD,
pp.141-145(1995)
38. Y.
39. H. Funaki and A. Nakagawa,”
Numeracal Prediction of
P-channel SOI LIGBT Electrical
Characteristics”,
Proc., of ISPSD, pp.350-353(1995)
40. I. Omura and A. Nakagawa,
“ An accurate PC aided
carrier lifetime determination technique from diode reverse recovery
waveform”, , Proc.,
of ISPSD, pp.422-426(1995)
41. M. Kitagawa, A. Nakagawa et al.,
“4500V IEGTs having
Switching Characteristics Superior to GTO”, Proc., of ISPSD, pp.486-491(1995)
42.
H.Funaki, Y. Yamaguchi, Y. Kawaguchi, Y. Terasaki, H. Mochizuki, A. Nakagawa, "High Voltage BiCDMOS Technology on Bonded 2um SOI
Integrating Vertical npn pnp, 60V-LDMOS and MPU, Capable of 200C
Operation ", IEEE
IEDM Tech Digest, p.967 (1995)
43. N.Yasuhara, H.Funaki, T.Matsudai, and A.Nakagawa, “Experimental Verification of Large Current
Capability of Lateral IEGTs on SOI”, Proc. of ISPSD,
pp.97-100(1996)
44. H.Funaki,
N.Yasuhara, and A.Nakagawa,
“
High Voltage Lateral MOS Thyristor Cascode Switch on
SOI ---Safe Operation Area of SOI-Resurf
Devices---“, Proc. of ISPSD,
pp.101-104(1996)
45. M.Kitagawa,
K.Matsushita, and A.Nakagawa, “High-Voltage Emitter Short Diode(ESD)”
Jpn.J.Appl.Phys.Vol.35 pp.5998-6002 (1996)
46. H. Funaki, T.
Matsudai, A. Nakagawa N. Yasuhara and Y. Yamaguchi, “MULTI-CHANNEL SOI LATERAL IGBTS WITH LARGE
SOA” Proc., of ISPSD,
pp.33-36(1997)
47. T. Matsudai and
H. Funaki and A. Nakagawa, “A Safe Operating Area
Model for SOI Lateral IGBTs” Proc., of ISPSD,
pp.41-44(1997)
48.
M.Kitagawa and A.Nakagawa, “Study of 4.5 kV MOS-Power Device with Injection-Enhanced Trench
Gate Structure
”, Jpn.J.Appl. Phys Vol.36,
pp1411-1414(1997)
49. Y.Kawaguchi, Y.Yamaguchi, H.Funaki, Y.Terazaki, and
A.Nakagawa, “0.8
mm CMOS Process Compatible 60-100 mW mm2 Power MOSFET on Bonded SOI
” , Jpn. J Appl.phys.,Vol.36
pp.1513-1518(1997)
50. H. Funaki, Y. Yamaguchi, K. Hirayama
and A. Nakagawa, “New 1200V MOSFET Structure on SOI with SIPOS
Shielding Layer” Proc., of ISPSD,
pp.25-28(1998)
51. H. Funaki, Y. Yamaguchi, K. Hirayama and
A. Nakagawa, “Lateral Diode Design Optimization for High
Ruggedness and Low Temperature Dependence of Reverse Recovery
Characteristics” Proc., of ISPSD,
pp.33-36(1998)
52. K. Kinoshita, Y. Kawaguchi, and A. Nakagawa, “A New Adaptive Resurf Concept for 20V LDMOS without
Breakdown Voltage Degradation at High Current”, Proc., of ISPSD,
pp.65-68(1998)
53. K. Kinoshita, Y. Kawaguchi, T. Sano and A. Nakagawa, “20V LDMOS Optimized for High Drain Current ConditionWhich is better, n-epi or p-epi” Proc. of ISPSD’99,
pp.59-62(1999)
54. Y.
mm2 Low On-Resistance
Novel Structure Trench Gate LDMOS”, Extended Abstract of SSDM, pp.120-121
(1999)
55. T. Matsudai, T. Kojima and A. Nakagawa, “Electrical Characteristics of Polysilicon CMOS Analog and Driver Circuits for Intelligent
IGBTs”, Extended Abstract of SSDM,
pp.94-95(1999)
56. Y.
57. Y.
58. Y.
59. T. Matsudai, H. Nozaki, S. Umekawa, M. Tanaka and M. Kobayashi, H. Hattori and A.
Nakagawa, “Advanced 60um Thin 600V Punch-Through IGBT Concept
for Extremely Low Forward Voltage and Low Turn-off Loss”, Proc.
of ISPSD, pp.441-444(2001)
60. T. Matsudai and A. Nakagawa, “Ultra High Switching Speed 600V Thin Wafer PT-IGBT
Based on New Turn-off Mechanism”, Proc. of ISPSD,
pp.285-288(2002)
61. S. Ono, Y. Kawaguchi, and A. Nakagawa, “30V New Fine Trench MOSFET with Ultra Low
On-Resistance” Proc. of ISPSD(2003), pp.28-31
62. Tomoko Matsudai, Masanori Tsukuda, Shinichi Umekawa,
Masahiro Tanaka and Akio Nakagawa, “New Anode Design Concept of 600V Thin Wafer PT-IGBT
with Very Low Dose P-buffer and Transparent P-emitter” Proc. of
ISPSD(2003), pp.75-78
63. Norio Yasuhara, Kenichi
Matsushita, Kazuya Nakayama, Bungo Tanaka, Shinichi Hodama, Akio Nakagawa and Kazutoshi
Nakamura, “Low Gate Charge 30 V N-channel LDMOS for DC-DC
Converters” Proc. of ISPSD(2003), pp.186-189
64. Toshiro Kubota, Kiminori Watanabe, Kumiko Karouji, Mitsuru Ueno,
Yasuko Anai, Yusuke Kawaguchi and Akio Nakagawa, “Cost-Effective Approach in LDMOS with Partial 0.35µm
Design into Conventional 0.6µm Process”, Proc. of ISPSD(2003),
pp.245-248
65. Mitsuhiko Kitagawa, Keiko Kawamura,
Kazuyoshi Furukawa, Nobuichi Kuramochi,
Akio Nakagawa and Yoshiaki Aizawa, “Ultra Low Cout×Ron Photo-relay using Depleted Drift
Layer in Thin Film SOI” Proc. of ISPSD(2003), pp.370-373
66. Taizo Yamane, Sadao
Ikeda and Akio Nakagawa, “Three-Phase Sinusoidal Current PWM Brushless Motor
Driver ICs”, Proc. of ISPSD(2004), pp.147-150
67. Syotaro Ono, Yoshihiro Yamaguchi,
Yusuke Kawaguchi, and Akio Nakagawa, “30V Sub-micron Shallow Junction Planar-MOSFET for
DC-DC Converters”, Proc. of ISPSD(2004), pp.401-404
68. Kazutoshi Nakamura, Toshiyuki Naka,
Kenichi Matsushita, Tomoko Matsudai, Norio Yasuhara Koichi Endo, Fumito
Suzuki, and Akio Nakagawa, "Optimization of
5V power devices based on CMOS for hot-carrier degradation", Proc.
of ISPSD(2005), pp.335-338
69. Yusuke Kawaguchi, Tomohiro Kawano, Hiroshi Takei, Syotaro Ono and Akio Nakagawa, "Multi ChipModule with Minimum Parasitic Inductance for New Generation Voltage
Regulator", Proc. of ISPSD(2005), pp.371-374
70. Syotaro Ono, Yoshihiro Yamaguchi, Noboru
Matsuda, Akio Takano, Miwako Akiyama,
Yusuke Kawaguchi, and Akio Nakagawa, "
High density MOSBD (UMOS
with built-in Trench Schottky Barrier Diode) for Synchronous Buck
Converters
", Proc. of ISPSD(2006),
pp.77-80
71. Nakamura, K.;
Matsushita, K.; Yasuhara, N.; Endo, K.; Suzuki, F.; Takahashi, M.; Nakagawa, A.,
"10A 12V
1 chip DC/DC converter IC using bump technology
," Bipolar/BiCMOS Circuits and Technology Meeting, 2006
, pp.1-4, 2006
72. Nakamura, K.; Matsushita,
K.; Naka, T.; Ikeda, Y.; Yasuhara, N.; Endo, K.; Suzuki, F.; Takahashi, M.;
Yamaguchi, M.; Nakagawa, A., "Demonstration of high frequency and 10A operation in 12V 1 chip
DC/DC converter IC using bump technology
," Power Semiconductor Devices and IC's, 2007.
ISPSD '07, pp.45-48, 2007
73. Kawaguchi, Y.; Yamaguchi, Y.; Kanie, S.; Baba, A.;
Nakagawa, A., "Proposal of the method for high efficiency DC-DC converters and
the efficiency limit restricted by silicon properties
," Power
Electronics Specialists Conference, 2008. PESC 2008,
pp.147-152, 2008
74. Nakamura, K.; Naka, T.; Kamata, Y.; Taguchi, T.;
Shimizu, T.; Ikeda, Y.; Nakagawa, A.; Maksimovic, D., "10A 12V 1
chip digitally-controlled DC/DC converter IC with high resolution and high
frequency DPWM
," Power Electronics and Motion Control Conference, 2008. EPE-PEMC 2008,
pp.498-503, 2008
75. Nakamura, K.;
Naka, T.; Matsushita, K.; Matsudai, T.; Yasuhara, N.; Nakagawa, A., "ESD protection structure with novel trigger technique for LDMOS
based on BiCD process
," Power Semiconductor Devices &
IC's, 2009. ISPSD 2009, pp.227-230, 2009
76. Nakamura, K.; Naka, T.; Yasuhara, N.; Minohara,
D.; Tsurugai, T.; Nakagawa, A., "20A 5V
single chip DC-DC converter IC with 5mohm MOSFET switch
," Applied Power Electronics
Conference and Exposition, 2009. APEC 2009, pp.498-502,
2009
東芝レビュー
1. 山口好広、中川明夫、遠藤幸一 「５００Ｖ−１ＡワンチップインバータＩＣ」(500V-1A
One-chip Inverter IC)
東芝レビュー Vol.48,
No.1 (1993)
2.
岸敬二、中川明夫、歌川忠、東実、植竹義成、土門知一 「高周波GTOを使用した大形電子計算機用定電圧直流電源」”Constant-Voltage D-C Supply Equipment for Large Computer Using
High-Frequency GTO Thyristor”
東芝レビュー 31巻10号 (1976)
3. 中川明夫 「システムパワーIC実現のための高耐圧SOI技術」 ”High-Voltage SOI Power IC Technology”
東芝レビューVol.52,
No.2 (1997)
4. 倉田衛、中川明夫、吉田二朗 「パワーデバイスのCAD」 ”Computer-Aided Design for Power Device”
東芝レビュー 36巻7号 (1981)
5. 中川明夫、歌川忠、塚越恒男,
倉田衛,
新井春江 「低損失高速ダイオード」”Low-Loss High-Speed Diodes”
東芝レビュー 34巻11号 (1979)
6. 中川明夫、新保優、大橋弘通 「Ｓｉ直接接合技術を用いたバイポーラ形MOSFET」”Bipolar-Mode MOSFETs Fabricated By
Silicon-Wafer Direct Bonding”
東芝レビュー４１巻１２号（１９８６）
7.
中川明夫、四戸孝 「ますます性能を上げるディスクリート半導体技術」 東芝レビュー 55巻、No.1(2000)
8.
A.Nakagawa, H.Ohashi, and K.Muramoto “Non-Latch-up Bipolar-Mode TM
MOSFETs with Large-Current Capacity” TOSHIBA REVIEW No. 152 SUMMER
(1985)
9. A.Nakagawa, K.Imamura,
and K.Furukawa “1,800 V Bipolar-mode MOSFETs (IGBT)” Toshiba Review Vol.161 AUTUMN
(1987)